[PCIe] Power Management - 4 - L1 Sub state

 

 

 

5.5. L1 PM Substates

 

L1 PM Substates establish a Link power management regime that creates lower power substates of the L1 Link state (see Figure 5-9), and associated mechanisms for using those substates. The L1 PM Substates are:

 

L1.0 substate

• The L1.0 substate corresponds to the conventional L1 Link state. This substate is
  entered whenever the Link enters L1. The L1 PM Substate mechanism defines
  transitions from this substate to and from the L1.1 and L1.2 substates. 
• The Upstream and Downstream Ports must be enabled to detect Electrical Idle exit as required in Section 4.2.6.7.2.

L1.1 substate

• Link common mode voltages are maintained.
• Uses a bidirectional( 양방향 즉, Host와 Device 양쪽에서 컨트롤 가능한) open-drain clock request (CLKREQ#) signal for entry to and exit from this state
• The Upstream(End Point) and Downstream Ports(Switch) are not required to be enabled to detect Electrical 
  Idle. (전기적 유휴 상태를 확인하기 위해 , upstram port 와 downstream port 를 활성화 하지 않아도 된다.)

L1.2 substate

• Link common mode voltages are not required to be maintained ( L1.1과 다른 부분)
• Uses a bidirectional open-drain clock request (CLKREQ#) signal for entry to and exit 
  from this state.
• The Upstream and Downstream Ports are not required to be enabled to detect electrical 
  idle (EI).

 

Ports that support L1 PM Substates must not require a reference clock while in L1 PM Substates other than L1.0. 

 

Ports that support the L1.2 substate for ASPM L1 must support Latency Tolerance Reporting (LTR).

 

• When enabled, the L1 PM Substates mechanism applies the following additional requirements to the CLKREQ# signal:The CLKREQ# signal must be supported as a bi-directional open drain signal by both the Upstream(Endpoint) and Downstream Ports(Switch) of the Link. Each Port must have a unique 20 instance of the signal, and the Upstream and Downstream Port CLKREQ# signals must be connected.
• It is permitted for the Upstream Port(Endpoint) to de-assert CLKREQ# (High) when the Link is in the PCI-PM L1 or ASPM L1 states, or when the Link is in the L2/L3 Ready pseudo-state; CLKREQ# must be asserted by the Upstream Port(Host) when the Link is in any other state.
• All other specifications related to the CLKREQ# signal that are not specifically defined or modified by L1 PM Substates continue to apply. (L1 PM 하위 상태에 의해 구체적으로 정의되거나 수정되지 않은 CLKREQ# 신호와 관련된 다른 모든 사양은 계속 적용됩니다.-> 즉 그 값들이 변경되지 않는다. )

 

If these requirements cannot be satisfied in a particular system, then L1 PM Substates must not be enabled

 

For an Upstream component(Switch) the connection topologies for the CLKREQ# signal can vary. A few examples of CLKREQ# connection topologies are described below. For the Downstream component(Endpoint) these cases are essentially the same, however from the Upstream component’s perspective, there are some key differences that are described below

 

Example 1: Single Downstream Port with a single PLL connected to a single Upstream Port (see Figure 5-10).

In this platform configuration the Upstream component (A) has only a single CLKREQ# signal. The Upstream and Downstream Ports’ CLKREQ# (A and B) signals are connected to each other. In this case, Upstream component (A), must assert CLKREQ# signal whenever it requires a reference clock.

 

Avoiding Unintended Interactions Between L1 PM Substates and the LTSSM (L1 PM 하위 상태와 LTSSM 간의 의도하지 않은 상호 작용 방지)

 

It is often the case that implementation techniques which save power will also increase the latency to return to normal operation. When implementing L1 PM Substates, it is important for the implementer to ensure that any added delays will not negatively interact with other elements of the platform. It is particularly important to ensure that LTSSM timeout conditions are not unintentionally triggered. (구현자는 추가된 지연이 플랫폼의 다른 요소와 부정적인 상호 작용을 하지 않도록 하는 것이 중요합니다.)  Although typical implementations will not approach the latencies that would cause such interactions, the responsibility lies with the implementor to ensure that correct overall operation is achieved.

 

5.5.1. Entry conditions for L1 PM Substates and L1.0 Requirements

 

The Link is considered to be in ASPM L1.0 when the L1 PM Substate is in L1.0 and LTSSM entered L1 through ASPM.

The following rules define how the L1.1 and L1.2 substates are entered:

• Both the Upstream and Downstream Ports must monitor the logical state of the CLKREQ# signal.
• When in ASPM L1.0 and the ASPM L1.2 Enable bit is Set, the L1.2 substate must be entered when CLKREQ# is de-asserted and all of the following conditions are true
  • the reported snooped LTR value is greater than or equal to the value set by the LTR_L1.2_THRESHOLD Value and Scale fields, or there is no snoop service latency requirement
  • the reported non-snooped LTR value is greater than or equal to the value set by the LTR_L1.2_THRESHOLD Value and Scale fields, or there is no non-snoop service latency requirement
• When in ASPM L1.0 and the ASPM L1.1 Enable bit is Set, the L1.1 substate must be entered when CLKREQ# is de-asserted and the conditions for entering the L1.2 substate are not satisfie

 

When the entry conditions for L1.2 are satisfied, the following rules apply:

• Both the Upstream and Downstream Ports must monitor the logical state of the CLKREQ# 
  input signal.
• An Upstream Port(Host)  must not de-assert CLKREQ# until the Link has entered L1.0.
• It is permitted for either Port to assert CLKREQ# to prevent the Link from entering L1.2. (링크가 L1.2로 진입하는 것을 막기 위해 호스트와 디바이스 두 포트 모두 CLKREQ#을 LOW로 내리 까는 것을 허용합니다.)
• A Downstream Port intending to block entry into L1.2 must assert CLKREQ# before the Link 
  enters L1 (L1.2로의 진입을 차단하려는 다운스트림 포트는 - 즉 디바이스는- 링크가 L1으로 진입하기 전에 CLKREQ#를 Low 로 내리 깔아야 합니다.)
• When CLKREQ# is de-asserted the Ports enter the L1.2.Entry substate of L1.2. (CLKREQ#이 High 로 들리면, 포트는 L1.2의 L1.2.Entry 하위 상태로 들어갑니다.)

If a Downstream Port(디바이스) is in ASPM L1.0 and ASPM L1.1 Enable and/or ASPM L1.2 Enable are Set, and the Downstream Port initiates an exit to Recovery without having entered L1.1 or L1.2, the Downstream Port must assert CLKREQ# until the Link exits Recovery. (Downstream Port가 L1.1 또는 L1.2에 진입하지 않고 Recovery로 빠져나가는 경우, Downstream Port 는 링크가 복구를 종료할 때까지 CLKREQ#을 내리깔고 있어야 합니다 )

 

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5.5.2. L1.1 Requirements

 

Both Upstream and Downstream Ports are permitted to deactivate mechanisms for electrical idle (EI) exit detection and Refclk activity detection if implemented, however both ports must maintain common mode. (업스트림 및 다운스트림 포트 모두 EI(전기 유휴) 종료 감지 및 Refclk 활동 감지(구현된 경우)를 위한 메커니즘을 비활성화할 수 있지만 두 포트 모두 공통 모드를 유지해야 합니다.)

 

5.5.2.1. Exit from L1.1

If either the Upstream or Downstream Port needs to initiate exit from L1.1, it must assert CLKREQ# until the Link exits Recovery. The Upstream Port must assert CLKREQ# on entry to Recovery, and must continue to assert CLKREQ# until the next entry into L1, or other state allowing CLKREQ# de-assertion.

 

Next state is L1.0 if CLKREQ# is asserted.

• The Refclk will eventually be turned on as defined in the PCI Express Mini CEM spec, 
  which may be delayed according to the LTR* advertized by the Upstream Port

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Latency Tolerance Reporting (LTR) Mechanism

 

The Latency Tolerance Reporting (LTR) mechanism enables Endpoints to report their service latency requirements for Memory Reads and Writes to the Root Complex, so that power management policies for central platform resources (such as main memory, RC internal interconnects, and snoop resources) can be implemented to consider Endpoint service requirements. The LTR Mechanism does not directly affect Link power management or Switch internal power management, although it is possible that indirect effects will occur.

 

The implications of “latency tolerance” will vary significantly between different device types and implementations. When implementing this mechanism, it will generally be desirable to consider if service latencies impact functionality or only performance, if performance impacts are linear, and how much it is possible for the device to use buffering and/or other techniques to compensate for latency sensitivities.

 

The Root Complex is not required to honor the requested service latencies, but is strongly encouraged to provide a worst case service latency that does not exceed the latencies indicated by the LTR mechanism.

 

LTR support is discovered and enabled through reporting and control registers described in Chapter 7. Software must not enable LTR in an Endpoint unless the Root Complex and all intermediate Switches indicate support for LTR. Note that it is not required that all Endpoints support LTR to permit enabling LTR in those Endpoints that do support it. When enabling the LTR mechanism in a hierarchy, devices closest to the Root Port must be enabled first.

 

If an LTR Message is received at a Downstream Port that does not support LTR or if LTR is not enabled, the Message must be treated as an Unsupported Request.

No-Snoop Latency and Snoop Latency: As shown in Figure 6-15, these fields include a Requirement bit that indicates if the device has a latency requirement for the given type of Request. If the Requirement bit is Set, the LatencyValue and LatencyScale fields describe the latency requirement. If the Requirement bit is Clear, there is no latency requirement and the LatencyValue and LatencyScale fields are ignored. With any LTR Message transmission, it is permitted for a device to indicate that a requirement is being reported for only no-snoop Requests, for only snoop Requests, or for both types of Requests. It is also permitted for a device to indicate that it has no requirement for either type of traffic, which it does by clearing the Requirement bit in both fields. 

 

 

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5.5.3 L1.2 Requirements

All Link and PHY state must be maintained during L1.2, or must be restored upon exit using implementation-specific meanss and the LTSSM and corresponding Port state upon exit from L1.2 must be indistinguishable from the L1.0 LTSSM and Port state.(모든 링크 및 PHY 상태는 L1.2 동안 유지되어야 하거나 구현별 수단을 사용하여 종료 시 복원되어야 하며 L1.2 종료 시 LTSSM 및 해당 포트 상태는 L1.0 LTSSM 및 포트 상태와 구별할 수 없어야 합니다.)

 

L1.2 has additional requirements that do not apply to L1.1. These requirements are documented in this section.

L1.2 has three substates, which are defined below (see Figure 5-14).

 

5.5.3.1. L1.2.Entry

L1.2.Entry is a transitional state on entry into L1.2 to allow time for Refclk to turn off and to ensure both Ports have observed CLKREQ# de-asserted. The following rules apply to L1.2.Entry:

(L1.2 Entry 는 L1.2로 전환하는 생태로, Refclk이 꺼지고, upstriming, downstriming ports 의 CLKREQ# de-asserted 상태를 확인 하는 것을 위한 시간이다. L1.2.Entry에는 다음 규칙이 적용됩니다.)

• Both Upstream and Downstream Ports continue to maintain common mode.
• Both Upstream and Downstream Ports may turn off their electrical idle (EI) exit detect circuitry. (EI(전기 유휴) 출구 감지 회로를 끌 수 있습니다.)
• The Upstream and Downstream Ports must not assert CLKREQ# in this state
• Refclk must be turned off within TL1O_REFCLK_OFF.
• Next state is L1.0 if CLKREQ# is asserted, else the next state is L1.2.Idle after waiting for TPOWER_OFF

Note that there is a boundary condition which can occur when one Port asserts CLKREQ# shortly after the other Port de-asserts CLKREQ#(다른 포트들이 CLKREQ# 를 de-assert 한 후 얼마 지나지 않아 한 포트가 CLKREQ#를 assert 한 경우), but before the first Port has observed CLKREQ# deasserted. (하지만 그 첫번째 포트가 CLKREQ#가 deasserted 된것을 확인하기 전에) This is an unavoidable boundary condition that implementations must handle correctly.  An example of this condition is illustrated in Figure 5-15. (이는 구현에서 올바르게 처리해야 하는 피할 수 없는 경계 조건입니다. 이 조건의 예가 그림 5-15에 나와 있습니다.)

 

5.5.3.2. L1.2.Idle

When requirements for the entry into L1.2.Idle state (see Section 5.5.1) have been satisfied then the Ports enter the L1.2.Idle substate. The following rules apply in L1.2.Idle:

• Both Upstream and Downstream Ports may power-down any active logic, including circuits required to maintain common mode.
• The PHY of both Upstream and Downstream Ports may have their power removed.

The following rules apply for L1.2.Idle state when using the CLKREQ#-based mechanism:

• If either the Upstream or Downstream Port needs to exit L1.2, it must assert CLKREQ# after ensuring that TL1.2 has been met. (TL1.2가 충족되었는지 확인한 후 CLKREQ#을 어설션해야 합니다.)
• If the Downstream Port is initiating exit from L1, it must assert CLKREQ# until the Link exits Recovery. (링크가 복구를 종료할 때까지 CLKREQ#을 어설션해야 합니다.) The Upstream Port must assert CLKREQ# on entry to Recovery, and must continue to assert CLKREQ# until the next entry into L1(업스트림 포트는 복구 진입 시 CLKREQ#을 어설션해야 하며 L1으로의 다음 진입까지 계속해서 CLKREQ#을 어설션해야 합니다.), or other state allowing CLKREQ# deassertion.
• If the Upstream Port is initiating exit from L1, it must continue to assert CLKREQ# until the next entry into L1, or other state allowing CLKREQ# de-assertion.
• Both the Upstream and Downstream Ports must monitor the logical state of the CLKREQ# input signal.
• Next state is L1.2.Exit if CLKREQ# is asserted.

5.5.3.3. L1.2.Exit

This is a transitional state on exit from L1.2 to allow time for both devices to power up. In L1.2.Exit, the following rules apply:

• The PHYs of both Upstream and Downstream Ports must be powered.
• It must not be assumed that common mode has been maintained. (공통 모드가 유지되었다고 가정해서는 안 됩니다.)

5.5.3.3.1. Exit from L1.2

The following rules apply for L1.2 Exit using the CLKREQ#-based mechanism:

• Both Upstream and Downstream Ports must power up any circuits required for L1.0, including circuits required to maintain common mode.
• The Upstream and Downstream Ports must not change their driving state of CLKREQ# in this state. (asserted)
• Refclk must be turned on no earlier than TL1O_REFCLK_ON minimum time, and may take up to the amount of time allowed according to the LTR advertized by the Endpoint before becoming valid.
• Next state is L1.0 after waiting for TPOWER_ON
  • Common mode is permitted to be established passively during L1.0, and actively during Recovery. In order to ensure common mode has been established, the Downstream Port must maintain a timer, and the Downstream Port must continue to send TS1 training sequences until a minimum of TCOMMONMODE has elapsed since the Downstream Port has started transmitting TS1 training sequences and has detected electrical idle exit on any Lane of the configured Link.

Figure 5-16 illustrates the signal relationships and timing constraints associated with L1.2 entry and Upstream Port initiated exit.

Figure 5-17 illustrates the signal relationships and timing constraints associated with L1.2 entry and Downstream Port initiated exit.

 

 

5.5.4. L1 PM Substates Configuration

L1 PM Substates is considered enabled on a Port when any combination of the ASPM L1.1 Enable, ASPM L1.2 Enable, bits associated with that Port are Set. (ASPM L1.1 활성화, ASPM L1.2 활성화, 해당 포트와 관련된 비트의 조합이 설정되면 L1 PM 하위 상태는 포트에서 활성화된 것으로 간주됩니다.)

 

An L1 PM Substate enable bit must only be Set in the Upstream and Downstream Ports on a Link when the corresponding supported capability bit is Set by both the Upstream and Downstream Ports on that Link, otherwise the behavior is undefined. (어떠한 L1 PM Substate enable bit 이 해당 link에 물린 Upstream, Downstream ports 모두에 적용 되어야 한다. 그렇지 않을 경우 동작이 정의되지 않는다)

 

The Setting of any enable bit must be performed at the Downstream Port before the corresponding bit is permitted to be Set at the Upstream Port. (설정시 Downstream port 먼저 설정) If any L1 PM Substates enable bit is at a later time to be cleared, the enable bit(s) must be cleared in the Upstream Port before the corresponding enable bit(s) are permitted to be cleared in the Downstream Port (설정 해제시 Upstream port 먼저 해제)

1. Downstream port(Switch) Enable 

2. Upsteam port(Endpoint) Enable

3. L1 Sub PM

4. Upstream port(Endpoint) disable 

5. Downstream port(Switch) disable 

4. L1.0

 

If setting the enable bits for ASPM L1 PM Substates, both ports must be configured as described in this section while ASPM L1 is disabled. (ASPM L1 PM 하위 상태에 대한 활성화 비트를 설정할때,  ASPM L1이 비활성화된 동안,  두 포트 모두 이 섹션에 설명된 대로 구성되어야 합니다.)

 

Prior to setting the enable bit for L1.2, the values for TPOWER_ON, Common_Mode_Restore_Time, and, if the ASPM L1.2 Enable bit is to be Set, the LTR_L1.2_THRESHOLD (both Value and Scale fields) must be programmed.

(L1.2에 대한 활성화 비트를 설정하기 전에 

1, TPOWER_ON,

2, Common_Mode_Restore_Time의 값 및

3, ASPM L1.2 활성화 비트를 설정하려는 경우

LTR_L1.2_THRESHOLD(값 및 스케일 필드 모두)를 프로그래밍 해야 합니다. )

 

The TPOWER_ON and Common_Mode_Restore_Time fields must be programmed to the appropriate values based on the components and AC coupling capacitors used in the connection linking the two components. The determination of these values is design implementation specific. (TPOWER_ON 및 Common_Mode_Restore_Time 필드는 두 구성 요소를 연결하는 연결에 사용되는 구성 요소 및 AC 커플링 커패시터를 기반으로 적절한 값으로 프로그래밍되어야 합니다. 이러한 값의 결정은 설계 구현에 따라 다릅니다.)

 

When both the ASPM L1.2 Enable bit is cleared, it is not required to program the TPOWER_ON, Common_Mode_Restore_Time, and LTR_L1.2_THRESHOLD Value and Scale fields, and hardware must not rely on these fields to have any particular values.

 

When programming LTR_L1.2_THRESHOLD Value and Scale fields, identical values must be programmed in both Ports.

 

5.5.5. L1 PM Substates Timing Parameters